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CYS25G0101DX
SONET OC-48 Transceiver
Features
* * * * * * * * * SONET OC-48 operation Bellcore and ITU jitter compliance 2.488-GBaud serial signaling rate Multiple selectable loopback/loop-through modes Single 155.52-MHz reference clock Transmit FIFO for flexible data interface clocking 16-bit parallel-to-serial conversion in transmit path Serial-to-16-bit parallel conversion in receive path Synchronous parallel interface -- LVPECL-compliant data recovery operations in a single chip, optimized for full SONET compliance. Transmit Path New data is accepted at the 16-bit parallel transmit interface at a rate of 155.52 MHz. This data is passed to a small integrated FIFO to allow flexible transfer of data between the SONET processor and the transmit serializer. As each 16-bit word is read from the transmit FIFO, it is serialized and sent out the high-speed differential line driver at a rate of 2.488 Gbits/second. Receive Path As serial data is received at the differential line receiver, it is passed to a clock and data recovery (CDR) PLL, which extracts a precision low-jitter clock from the transitions in the data stream. This bit-rate clock is then used to sample the data stream and receive the data. Every 16-bit-times, a new word is presented at the receive parallel interface along with a clock. Parallel Interface The parallel I/O interface supports high-speed bus communications using HSTL signaling levels to minimize both power consumption and board landscape. The HSTL outputs are capable of driving unterminated transmission lines of less than 70 mm, and terminated 50 transmission lines of more than twice that length. The CYS25G0101DX Transceiver's parallel HSTL I/O can also be configured to operate at LVPECL signaling levels. This can all be done externally by changing VDDQ, VREF, and creating a simple circuit at the termination of the transceiver's parallel output interface. Clocking The source clock for the transmit data path is selectable from either the recovered clock or an external BITS (Building Integrated Timing Source) reference clock. The low jitter of the CYS25G0101DX
TXD[15:0] TXCLKI FIFO_RST FIFO_ERR TXCLKO RXD[15:0] RXCLK LOOPTIME DIAGLOOP LOOPA LINELOOP RESET PWRDN LOCKREF LFI
-- HSTL-compliant * Internal transmit and receive phase-locked loops (PLLs) * Differential CML serial input -- 50-mV input sensitivity * -- 100 Internal termination and DC-restoration Differential CML serial output -- Source matched for 50 transmission lines (100 differential transmission lines) Direct interface to standard fiber-optic modules Less than 1.0W typical power 120-pin 14 mm x 14 mm TQFP Standby power-saving mode for inactive loops 0.25 BiCMOS technology
* * * * *
Functional Description
The CYS25G0101DX SONET OC-48 Transceiver is a communications building block for high-speed SONET data communications. It provides complete parallel-to-serial and serial-to-parallel conversion, clock generation, and clock and
System or Telco Bus
SONET Data Processor
Transmit Data Interface
16
REFCLK
2
Host Bus Interface
Receive Data Interface
16
155.52 MHz BITS Time Reference
Data & Clock Direction Control
IN+ IN- SD OUT- OUT+
Serial Data
Serial Data
RD+ RD- SD TD- TD+
Optical XCVR
Optical Fiber Links
Status and System Control
Figure 1. CYS25G0101DX System Connections
Cypress Semiconductor Corporation Document #: 38-02009 Rev. *J
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 Revised December 30, 2002
CYS25G0101DX
CDR PLL allows loop-timed operation of the transmit data path while still meeting all Bellcore and ITU jitter requirements. Multiple loopback and loop-through modes are available for both diagnostic and normal operation. For systems containing redundant SONET rings that are maintained in standby, the CYS25G0101DX may also be dynamically powered down to conserve system power.
Logic Block Diagram
(155.52 MHz) TXCLKI TXD[15:0] FIFO_RST 16 16 Output Register
/16
FIFO_ERR
TXCLKO
(155.52 MHz) REFCLK
(155.52 MHz) RXCLK
RXD[15:0]
Input Register
TX PLL X16
FIFO
/16
Shifter Recovered Bit-Clock RX CDR PLL Lock-to-Ref Retimed Data
TX Bit-Clock Shifter
LOOPTIME DIAGLOOP
LINELOOP LOOPA
Lock-to-Data/ Clock Control Logic
OUT
PWRDN LOCKREF
SD
LFI
RESET
IN
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CYS25G0101DX
Pin Configuration[1, 2]
120-pin Thin Quad Flatpack Pin Configuration
VCCQ \NC* RXCP1 RXCN1 VSSQ \NC* VCCQ
NC VSSQ \NC* RXCP2 RXCN2
Top View
VSSQ VCCQ IN+ IN- VSSQ CM_SER VCCQ VCCQ VSSQ VCCQ
O U T+ O U T-
NC NC VSSQ NC VSSQ VCCQ NC NC
120
119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95
94 93 92 91
NC
LFI RESET DIAGLOOP LINELOOP LOOPA VSSN VCCN VSSN VSSN SD LOCKREF RXD[0] RXD[1] RXD[2] RXD[3] VSSN VDDQ RXD[4] RXD[5] RXD[6] RXD[7] VSSN VDDQ RXCLK VSSN VDDQ NC NC NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
CYS25G0101DX
90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75
NC VCCQ VSSQ REFCLK+ REFCLK- NC LOOPTIME PWRDN VSSN VCCN VSSN TXCLKO VSSN VDDQ TXD[0] TXD[1] TXD[2] TXD[3] VCCQ VSSQ VCCN VSSN TXD[4] TXD[5] TXD[6] TXD[7] TXD[8] TXD[9] TXD[10] TXD[11]
74 73 72 71 70 69 68 67 66 65 64 63 62 61 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
VSSQ
VCCQ NC NC VC CQ RXD[8]
Notes: 1. No connect (NC) pins must be left unconnected or floating. Connecting any of these pins to the positive or negative power supply may cause improper operation or failure of the device. 2. Pins 113 and 119 can be either no connect or VSSQ. Use VSSQ for compatibility with next generation of OC-48 SERDES devices. Pin 116 can be either no connect or VCCQ. Use VCCQ for compatibility with next generation of OC-48 SERDES devices.
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VSSN VD DQ RXD[12] RXD[13] RXD[14] RXD[15] VSSN VDDQ VCC N VSSN FIFO_ERR FIFO_RST TXD[15] TXD[14] TXD[13] TXD[12] TXCLKI VSSN VCC N VREF
VSSQ
RXD[9] RXD[10] RXD[11]
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CYS25G0101DX
Pin Descriptions
CYS25G0101DX OC-48 SONET Transceiver Pin Name TXD[15:0] TXCLKI I/O Characteristics Signal Description Transmit Path Signals HSTL inputs, Parallel Transmit Data Inputs. A 16-bit word, sampled by TXCLKI. TXD[15] is the most sampled by TXCLKI significant bit (the first bit transmitted). HSTL Clock input Parallel Transmit Data Input Clock. The TXCLKI is used to transfer the data into the input register of the serializer. The TXCLKI samples the data, TXD [15:0], on the rising edge of the clock cycle. Transmit Clock Output. Divide by 16 of the selected transmit bit-rate clock. It can be used to coordinate byte-wide transfers between upstream logic and the CYS25G0101DX. Reference Voltage for HSTL Parallel Input Bus. VDDQ/2.[3]
TXCLKO VREF
HSTL Clock output Input Analog Reference HSTL output, synchronous HSTL Clock output Analog Analog Analog Analog Analog
Receive Path Signals RXD[15:0] RXCLK CM_SER RXCN1 RXCN2 RXCP1 RXCP2 REFCLK Parallel Receive Data Output. These outputs change following RXCLK. RXD[15] is the most significant bit of the output word, and is received first on the serial interface. Receive Clock Output. Divide by 16 of the bit-rate clock extracted from the received serial stream. RXD [15:0] is clocked out on the falling edge of the RXCLK. Common Mode Termination. Capacitor shunt to VSS for common mode noise. Receive Loop Filter Capacitor (Negative) Receive Loop Filter Capacitor (Negative) Receive Loop Filter Capacitor (Positive) Receive Loop Filter Capacitor (Positive)
Device Control and Status Signals Differential LVPECL Reference Clock. This clock input is used as the timing reference for the transmit and input receive PLLs. A derivative of this input clock may also be used to clock the transmit parallel interface. The reference clock is internally biased allowing for an AC-coupled clock signal. LVTTL output Line Fault Indicator. When LOW, this signal indicates that the selected receive data stream has been detected as invalid by either a LOW input on SD, or by the receive VCO being operated outside its specified limits. Reset for all logic functions except the transmit FIFO. Receive PLL Lock to Reference. When LOW, the receive PLL locks to REFCLK instead of the received serial data stream. Signal Detect. When LOW, the receive PLL locks to REFCLK instead of the received serial data stream. The SD is to be connected to an external optical module to indicate a loss of received optical power. Transmit FIFO Error. When HIGH the transmit FIFO has either under or overflowed. When this occurs, the FIFO's internal clearing mechanism will clear the FIFO within 9 clock cycles. In addition, FIFO_RST must be activated at device power-up to ensure that the in and out pointers of the FIFO are set to maximum separation. Transmit FIFO Reset. When LOW, the in and out pointers of the transmit FIFO are set to maximum separation. FIFO_RST must be activated at device power-up to ensure that the in and out pointers of the FIFO are set to maximum separation. When the FIFO is being reset, the output data is a 1010... pattern. Device Power Down. When LOW, the logic and drivers are all disabled and placed into a standby condition where only minimal power is dissipated. Diagnostic Loopback Control. When HIGH, transmit data is routed through the receive clock and data recovery and presented at the RXD[15:0] outputs. When LOW, received serial data is routed through the receive clock and data recovery and presented at the RXD[15:0] outputs.
LFI
RESET LOCKREF SD
LVTTL input LVTTL input LVTTL input
FIFO_ERR
LVTTL output
FIFO_RST
LVTTL input
PWRDN
LVTTL input
Loop Control Signals DIAGLOOP LVTTL input
Note: 3. VREF equals to (VCC - 1.33)V if interfacing to a parallel LVPECL interface.
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CYS25G0101DX
CYS25G0101DX OC-48 SONET Transceiver (continued) Pin Name LINELOOP I/O Characteristics LVTTL input Signal Description Line Loopback Control. When HIGH, received serial data is looped back from receive to transmit after being reclocked by a recovered clock. When LINELOOP is LOW, the data passed to the OUT line driver is controlled by LOOPA. When both LINELOOP and LOOPA are LOW, the data passed to the OUT line driver is generated in the transmit shifter. Analog Line Loopback. When LINELOOP is LOW and LOOPA is HIGH, received serial data is looped back from receive input buffer to transmit output buffer, but is not routed through the clock and data recovery PLL. When LOOPA is LOW, the data passed to the OUT line driver is controlled by LINELOOP. Loop Time Mode. When HIGH, the extracted receive bit-clock replaces transmit bit-clock. When LOW, the REFCLK input is multiplied by 16 to generate the transmit bit clock. Differential Serial Data Output. This differential CML output (+3.3V referenced) is capable of driving terminated 50 transmission lines or commercial fiber-optic transmitter modules. Differential Serial Data Input. This differential input accept the serial data stream for deserialization and clock extraction. +3.3V supply (for digital and low-speed I/O functions) Signal and power ground (for digital and low-speed I/O functions) +3.3V quiet power (for analog functions) Quiet ground (for analog functions) +1.5V supply for HSTL outputs[4] the transmit FIFO has either under or overflowed. The FIFO can be externally reset to clear the error indication or if no action is taken, the internal clearing mechanism will clear the FIFO in nine clock cycles. When the FIFO is being reset, the output data is 1010. Transmit PLL Clock Multiplier The Transmit PLL Clock Multiplier accepts a 155.52-MHz external clock at the REFCLK input, and multiplies that clock by 16 to generate a bit-rate clock for use by the transmit shifter. The operating serial signaling rate and allowable range of REFCLK frequencies is listed in Table 7. The REFCLK phase noise limits to meet SONET compliancy are illustrated in Figure 5. The REFCLK input is a standard LVPECL input. Serializer The parallel data from the phase-align buffer is passed to the Serializer which converts the parallel data to serial data using the bit-rate clock generated by the Transmit PLL clock multiplier. TXD[15] is the most significant bit of the output word, and is transmitted first on the serial interface. Serial Output Driver The serial interface Output Driver makes use of high-performance differential Current Mode Logic (CML) to provide a source-matched driver for the transmission lines. This driver receives its data from the Transmit Shifters or the receive loopback data. The outputs have signal swings equivalent to that of standard LVPECL drivers, and are capable of driving AC-coupled optical modules or transmission lines.
LOOPA
LVTTL input
LOOPTIME Serial I/O OUT IN Power VCCN VSSN VCCQ VSSQ VDDQ
LVTTL input
Differential CML output Differential CML input Power Ground Power Ground Power
CYS25G0101DX Operation
The CYS25G0101DX is a highly configurable device designed to support reliable transfer of large quantities of data using high-speed serial links. It performs necessary clock and data recovery, clock generation, serial-to-parallel conversion, and parallel-to-serial conversion. CYS25G0101DX also provides various loopback functions.
CYS25G0101DX Transmit Data Path
Operating Modes The transmit path of the CYS25G0101DX supports 16-bit -wide data paths. Phase-Align Buffer Data from the input register is passed to a phase-align buffer (FIFO). This buffer is used to absorb clock phase differences between the transmit input clock and the internal character clock. Initialization of the phase-align buffer takes place when the FIFO_RST input is asserted LOW. When FIFO_RST is returned HIGH, the present input clock phase relative to TXCLKO is set. Once set, the input clock is allowed to skew in time up to half a character period in either direction relative to REFCLK (i.e., 180). This time shift allows the delay path of the character clock (relative to REFLCK) to change due to operating voltage and temperature while not effecting the desired operation. FIFO_RST is an asynchronous input. FIFO_ERR is the transmit FIFO Error indicator. When HIGH,
Note: 4. VDDQ equals VCC if interfacing to a parallel LVPECL interface.
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CYS25G0101DX
CYS25G0101DX Receive Data Path
Serial Line Receivers A differential line receiver, IN, is available for accepting the input serial data stream. The serial line receiver inputs can accommodate high wire interconnect and filtering losses or transmission line attenuation (VSE > 25 mV, or 50 mV peak-to-peak differential), and can be AC-coupled to +3.3V or +5V powered fiber-optic interface modules. The commonmode tolerance of these line receivers accommodates a wide range of signal termination voltages. Lock to Data Control Line Receiver routed to the clock and data recovery PLL is monitored for * status of signal detect (SD) pin * status of LOCKREF pin. This status is presented on the Line Fault Indicator (LFI) output, which changes asynchronously in the cases in which SD or LOCKREF go from HIGH to LOW. Otherwise, it changes synchronously to the REFCLK. Clock/Data Recovery The extraction of a bit-rate clock and recovery of data bits from received serial stream is performed by a Clock/Data Recovery (CDR) block. The clock extraction function is performed by high-performance embedded phase-locked loop (PLL) that tracks the frequency of the incoming bit stream and aligns the phase of the internal bit-rate clock to the transitions in the selected serial data stream. CDR accepts a character-rate (bit-rate * 16) reference clock on the REFCLK input. This REFCLK input is used to ensure that the VCO (within the CDR) is operating at the correct frequency (rather than some harmonic of the bit-rate), to improve PLL acquisition time, and to limit unlocked frequency excursions of the CDR VCO when no data is present at the serial inputs. Regardless of the type of signal present, the CDR will attempt to recover a data stream from it. If the frequency of the recovered data stream is outside the limits set by the range controls, the CDR PLL will track REFCLK instead of the data stream. When the frequency of the selected data stream returns to a valid frequency, the CDR PLL is allowed to track the received data stream. The frequency of REFCLK is required to be within 100 ppm of the frequency of the clock that drives the REFCLK signal of the remote transmitter to ensure a lock to the incoming data stream. For systems using multiple or redundant connections, the LFI output can be used to select an alternate data stream. When an LFI indication is detected, external logic can toggle selection of the input device. When such a port switch takes place, it is necessary for the PLL to reacquire lock to the new serial stream. External Filter The CDR circuit uses external capacitors for the PLL filter. A 0.1-F capacitor needs be connected between RXCN1 and RXCP1. Similarly a 0.1-F capacitor needs to be connected between RXCN2 and RXCP2. The recommended packages and dielectric material for these capacitors are 0805 X7R or 0603 X7R. Deserializer The CDR circuit extracts bits from the serial data stream and Document #: 38-02009 Rev. *J Page 6 of 15 clocks these bits into the Deserializer at the bit-clock rate. The Deserializer converts serial data into parallel data. RXD[15] is the most significant bit of the output word and is received first on the serial interface. Loopback/Timing Modes CYS25G0101DX supports various loopback modes, as described below. Facility Loopback (Line Loopback with Retiming) When the LINELOOP signal is set HIGH, the Facility Loopback mode is activated and the high-speed serial receive data (IN) is presented to the high-speed transmit output (OUT) after retiming. In Facility Loopback mode, the high-speed receive data (IN) is also converted to parallel data and presented to the low-speed receive data output pins (RXD[15:0]). The receive recovered clock is also divided down and presented to the low-speed clock output (RXCLK). Equipment Loopback (Diagnostic Loopback with Retiming) When the DIAGLOOP signal is set HIGH, transmit data is looped back to the RX PLL, replacing IN. Data is looped back from the parallel TX inputs to the parallel RX outputs. The data is looped back at the internal serial interface and goes through transmit shifter and the receive CDR. SD is ignored in this mode. Line Loopback Mode (Non-retimed Data) When the LOOPA signal is set HIGH, the RX serial data is directly buffered out to the transmit serial data. The data at the serial output is not retimed. Loop Timing Mode When the LOOPTIME signal is set HIGH, the TX PLL is bypassed and receive bit-rate clock is used for transmit side shifter. Reset Modes ALL logic circuits in the device can be reset using RESET and FIFO_RST signals. When RESET is set LOW, all logic circuits except FIFO are internally reset. When FIFO_RST is set LOW, the FIFO logic is reset. Power-down Mode CYS25G0101DX provides a global power-down signal PWRDN. When LOW, this signal powers down the entire device to a minimal power dissipation state. RESET and FIFO_RST signals should be asserted LOW along with PWRDN signal to ensure low power dissipation. LVPECL Compliance The CYS25G0101DX HSTL parallel I/O can be configured to LVPECL compliance with slight termination modifications. On the transmit side of the transceiver, the TXD[15:0] and TXCLKI can be made LVPECL compliant by setting VREF (reference voltage of a LVPECL signal) to VCC - 1.33V. To emulate an LVPECL signal on the receiver side, VDDQ needs to be set to 3.3V and the transmission lines need to be terminated with the Thevenin equivalent of Z at LVPECL ref. The signal is then attenuated using a series resistor at the driver end of the line to reduce the 3.3V swing level to an LVPECL swing level (see Figure 10). This circuit needs to be used on all 16 RXD[15:0] pins, TXCLKO, and RXCLK. The voltage divider has been calculated assuming the system is built with 50 transmission lines.
CYS25G0101DX
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................-65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C VCC Supply Voltage to Ground Potential ....... -0.5V to +4.2V VDDQ Supply Voltage to Ground Potential ..... -0.5V to +4.2V DC Voltage Applied to HSTL Outputs in High-Z State .....................................-0.5V to VDDQ + 0.5V DC Voltage Applied to Other Outputs in High-Z State .......................................-0.5V to VCC + 0.5V Output Current into LVTTL Outputs (LOW)..................30 mA DC Input Voltage....................................-0.5V to VCC + 0.5V Static Discharge Voltage ...........................................> 1100V (per MIL-STD-883, Method 3015) Latch-up Current .....................................................> 200 mA Table 1. DC Specifications--LVTTL Parameter LVTTL Outputs VOHT VOLT IOS LVTTL Inputs VIHT VILT IIHT IILT Capacitance CIN Input Capacitance VCC = Max., @ f = 1 MHz 5 pF Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Low = 2.1V, High = VCC + 0.5V Low = -3.0V, High = 0.8 VCC = Max., VIN = VCC VCC = Max., VIN = 0V 2.1 -0.3 VCC - 0.3 0.8 50 -50 V V
A A
Power-up Requirements Power supply sequencing is not required if you are configuring VDDQ=3.3volts and all power supplies pins are connected to the same 3.3 volt power supply. Power supply sequencing is required if you are configuring VDDQ=1.5volts. Power must be applied in the following sequence: VCC (3.3) followed by VDDQ (1.5). Power supply ramping may occur simultaneously as long as the VCC/VDDQ relationship is maintained.
Operating Range
Range Commercial Industrial Ambient Temperature 0C to +70C VDDQ 1.4V to 1.6V[4] 1.6V[4] VCC 3.3V 10% 3.3V 10%
-40C to +85C 1.4V to
Description Output HIGH Voltage Output LOW Voltage Output Short Circuit Current
Test Conditions VCC = Min., IOH = -10.0 mA VCC = Min., IOL = 10.0 mA VOUT = 0V
Min. 2.4
Max.
Unit V
0.4 -20 -90
V mA
Table 2. DC Specifications--Power Parameter Power ICC1 ISB Active Power Supply Current Standby Current 300 347 5 mA mA Description Test Conditions Typ. Max. Unit
Table 3. DC Specifications--Differential LVPECL Compatible Inputs (REFCLK) [5] Parameter VINSGLE VDIFFE VIEHH VIELL IIEH IIEL Capacitance CINE Input Capacitance 4 pF
Note: 5. See Figure 2 for differential waveform definition.
Description Input Single-ended Swing Input Differential Voltage Highest Input HIGH Voltage Lowest Input LOW Voltage Input HIGH Current Input LOW Current
Test Conditions
Min. 200 400 VCC - 1.2 VCC - 2.0
Max. 600 1200 VCC - 0.3 VCC - 1.45 750
Unit mV mV V V A A
VIN = VIEHH Max. VIN = VIELL Min. -200
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CYS25G0101DX
Table 4. DC Specifications--Differential CML[5] Parameter VOHC VOLC VDIFFOC VSGLCO VINSGLC VDIFFC VICHH VICLL Description Output HIGH Voltage (VCC Referenced) Output LOW Voltage (VCC Referenced) Output Differential Swing Output Single-ended Voltage Input Single-ended Swing Input Differential Voltage Highest Input HIGH Voltage Lowest Input LOW Voltage 1.2 Test Conditions Min. Max. Unit V V mV mV mV mV V V Transmitter CML-compatible Outputs 100 differential load VCC - 0.5 VCC - 0.15 100 differential load VCC - 1.2 VCC - 0.7 100 differential load 560 1600 100 differential load 280 25 50 800 1000 2000 VCC
Receiver CML-compatible Inputs
V (+ ) V SGL V (-) VD 0 .0 V V D IF F = V (+ )-V (-)
Figure 2. Differential Waveform Definition Table 5. DC Specifications--HSTL Parameter HSTL Outputs VOHH VOLH IOSH HSTL Inputs VIHH VILH IIHH IILH Capacitance CINH Input Capacitance VDDQ = max., @ f = 1 MHz 5 pF Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current VDDQ = max., VIN = VDDQ VDDQ = max., VIN = 0V VREF + 0.13 VDDQ + 0.3 -0.3 VREF - 0.1 50 -40 V V
A A
Description Output HIGH Voltage Output LOW Voltage Output Short Circuit Current
Test Conditions VCC = min., IOH= -4.0 mA VCC = min., IOL= 4.0 mA VOUT = 0V
Min. VDDQ - 0.4
Max.
Unit V
0.4 100
V mA
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CYS25G0101DX
AC Waveforms
3.0V Vth = 1.4V GND < 1 ns 2.0V 0.8V 3.0V 2.0V 0.8V Vth = 1.4V < 1 ns 80% 20% < 150 ps VICLL VICHH 80% 20% < 150 ps
(a) LVTTL Input Test Waveform
VIHH Vth = 0.75V VIHL < 1 ns < 1 ns 80% 20% 80% 20%
(b) CML Input Test Waveform
VIEHH 80% Vth = 0.75V 20% < 1.0 ns VIELL 80% 20% < 1.0 ns
(c) HSTL Input Test Waveform
(d) LVPECL Input Test Waveform
AC Test Loads
3.3V OUTPUT R1 = 330 R2 = 510 CL 10 pF (Includes fixture and probe capacitance) CL R2 R1 OUT+ OUT- RL RL = 100 OUTPUT R1 = 100 R2 = 100 CL 7 pF (Includes fixture and probe capacitance) 1.5V R1 CL R2
(a) TTL AC Test Load
(b) CML AC Test Load
(c) HSTL AC Test Load
AC Specifications
Table 6. AC Specifications--Parallel Interface Parameter tTS tTXCLKI tTXCLKID tTXCLKIR tTXCLKIF tTXDS tTXDH tTOS tTXCLKO tTXCLKOD tTXCLKOR tTXCLKOF tRS tRXCLK tRXCLKD tRXCLKR tRXCLKF tRXDS tRXDH tRXPD TXCLKI Period TXCLKI Duty Cycle TXCLKi Rise Time TXCLKi Fall Time Write Data Set-up to of TXCLKI Write Data Hold from of TXCLKI TXCLKO Frequency TXCLKO Period TXCLKO Duty Cycle TXCLKO Rise Time TXCLKO Fall Time RXCLK Frequency RXCLK Period RXCLK Duty Cycle RXCLK Rise Time[6] RXCLK Fall Time[6] Recovered Data Set-up with reference to of RXCLK Recovered Data Hold with reference to of RXCLK Valid Propagation Delay Description TXCLKI Frequency (must be frequency coherent to REFCLK) Min. 154.5 6.38 40 0.3 0.3 1.5 0.5 154.5 6.38 43 0.3 0.3 154.5 6.38 43 0.3 0.3 2.2 2.2 -1.0 1.0 156.5 6.47 57 1.5 1.5 156.5 6.47 57 1.5 1.5 Max. 156.5 6.47 60 1.5 1.5 Unit MHz ns % ns ns ns ns MHz ns % ns ns MHz ns % ns ns ns ns ns
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CYS25G0101DX
Table 7. AC Specifications--REFCLK[7] Parameter tREF tREFP tREFD tREFT tREFR tREFF REFCLK Input Frequency REFCLK Period REFCLK Duty Cycle REFCLK Frequency Tolerance -- (relative to received serial data)[8] REFCLK Rise Time REFCLK Fall Time Description Min. 154.5 6.38 35 -100 0.3 0.3 Max. 156.5 6.47 65 +100 1.5 1.5 Unit MHz ns % ppm ns ns
Table 8. AC Specifications-CML Serial Outputs Parameter tRISE tFALL Description CML Output Rise Time (20-80%, 100 balanced load) CML Output Fall Time (80-20%, 100 balanced load) Min. 60 60 Typical Max. 170 170 Unit ps ps
Table 9. Jitter Specifications Parameter tTJ-TXPLL tTJ-RXPLL Description Total Output Jitter for TX PLL (p-p)[9] Total Output Jitter for TX PLL (rms)
[9, 11]
Min.
Typical[10] Max.[10] 0.03 0.007 0.035 0.008 0.04 0.008 0.05 0.01
Unit UI UI UI UI
Total Output Jitter for RX CDR PLL (p-p)[9] Total Output Jitter for RX CDR PLL (rms)[9, 11]
Notes: 6. RXCLk rise time and fall times are measured at the 20 to 80 percentile region of the rising and falling edge of the clock signal. 7. The 155.52 MHz Reference Clock Phase Noise Limits for the CYS25G0101DX are illustrated in Figure 5. 8. +20 ppm is required to meet the SONET output frequency specification. 9. The RMS and P-to-P jitter values are measured using a 12-KHz to 20-MHz SONET filter. 10. Typical values are measured at room temperature and the Max. values are measured at 0 C. 11. This device passes the Bellcore specification from -10 C to 85 C.
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CYS25G0101DX
Jitter Waveforms
Figure 3. Jitter Transfer Waveform of CYS25G0101DX[12]
Figure 4. Jitter Tolerance Waveform of CYS25G0101DX[12]
Note: 12. The bench jitter measurements were performed using an Agilent Omni-bert SONET jitter tester.
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CYS25G0101DX
CYS25G0101DX Reference Clock Phase Noise Limits
-75
-85
-95
Phase Noise (dBc)
-105
-115
-125
-135
-145
-155 1,000
10,000
100,000
1,000,000
10,000,000
100,000,000
Frequency (Hz)
Figure 5. CYS25G0101DX Reference Clock Phase Noise Limits
Switching Waveforms
Transmit Interface Timing
tTXCLKI tTXCLKIDH tTXCLKIDL
TXCLKI
t TXDS tTXDH
TXD[15:0]
tTXCLKO tTXCLKODL tTXCLKODH
TXCLKO
Receive Interface Timing
tRXCLK tRXCLKDL tRXCLKDH
RXCLK
t RXPD
t RXDS
tRXDH
RXD[15:0]
Document #: 38-02009 Rev. *J
Page 12 of 15
CYS25G0101DX
Typical I/O Terminations
Limiting Amp 0.1 F
OUT+ OUT-
CYS25G0101DX Zo=50
IN+ 100 IN-
0.1 F
Zo=50
Figure 6. Serial Input Termination
CY S25G0101DX 0.1 F
OUT+ OUT-
Optical Module Zo=50
IN+ 100 IN-
0.1 F
Zo=50
Figure 7. Serial Output Termination[13]
CY S25G0101DX VDDQ=1.5V
HSTL OUTPU T
FRAMER Zo=50 100 100
HSTL INPUT
Figure 8. TXCLKO/ RXCLK Termination
CY S25G0101DX Zo=50 FRAMER
HSTL INPUT
HSTL OUTPU T
Figure 9. RXD[15:0] Termination
VDDQ=3.3V
RXD[15;0], RXCLK, TXCLKO OUTPUT
FRAMER VDDQ=3.3V 137 Zo=50 80.6 121 LVPECL INPUT
CY S25G0101DX
Figure 10. LVPECL-compliant Output Termination
Clock Oscillator Zo=50
LVPEC L OUTPUT
VCC 130 82 VCC 130 0.1uF 0.1uF
CY S25G0101DX
Zo=50
82
Refcloc k I nter nall y Biased
Figure 11. AC-Coupled Clock Oscillator Termination
Note: 13. Serial output of CYS25G0101DX is source matched to 50 transmission lines (100 differential transmission lines).
Document #: 38-02009 Rev. *J
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CYS25G0101DX
Clock Oscillator Zo=50
LVPEC L OUTPUT
VCC 130 82 VCC 130 82
CY S25G0101DX
Zo=50
Reference Cloc k Input
Figure 12. Clock Oscillator Termination
Ordering Information
Speed Standard Standard Ordering Code CYS25G0101DX-ATC CYS25G0101DX-ATI Package Name AT120 AT120 Package Type 120-pin TQFP 120-pin TQFP Operating Range Commercial Industrial
Package Diagram
120-pin Thin Quad Flatpack (14 x 14 x 1.4 mm) with Heat Slug AT120
51-85116-**
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-02009 Rev. *J
Page 14 of 15
(c) Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CYS25G0101DX
Document History Page
Document Title: CYS25G0101DX SONET OC-48 Transceiver Document Number: 38-02009 REV. ** *A *B ECN NO. 105847 108024 111834 Issue Date 03/22/01 06/20/01 12/18/01 Orig. of Change SZV AMV CGX Description of Change Change from Spec number: 38-00894 to 38-02009. Changed Marketing part number. Updated power specification in features and DC specs section. Changed pinout to be compatible with CYS25G0102DX in pin diagram and descriptions. Verbiage added or changed for clarity in pin descriptions section. Changed input sensitivity in Receive Data Path section, page 6. RXCLK rise time corrected to 0.3 nSec min. CML and LVPECL input waveforms updated in test load and waveform section. Diagrams replaced for clarity Figures 1-10. Added two Refclock diagrams Figures 9 and 10. Updated temperature range, static discharge voltage, and max total RMS jitter. Updated the single ended swing and differential swing voltage for Receiver CML compatible inputs. Created a separate table showing peak to peak and RMS jitter for both TX PLL and RX PLL. Added Industrial temperature spec to pages 8, 11, and 15. Added differential waveform definition. Added BGA pinout and package information. Changed LVTTL VIHT min. from 2.0 to 2.1 volts. Added phase noise limits data. Removed BGA pinout and package information. Removed references to CYS25G0102DX. Removed "Preliminary" from data-sheet Add power up requirements to Maximum Ratings information Revised power up requirements
*C *D
112712 113791
02/06/02 04/24/02
TME CGX
*E *F
115940 117906
05/22/02 09/06/02
TME CGX
*G
119267
10/17/02
CGX
*H *I *J
121019 122319 124438
11/06/02 12/30/02 02/13/03
CGX RBI WAI
Document #: 38-02009 Rev. *J
Page 15 of 15

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